Silicon pillar thickness

Abstract – The Si pillar thickness consequence on perpendicular dual gate MOSFET ( VDGM ) fabricated by implementing oblique revolving ion nidation ( ORI ) method is investigated. For this intent, several Si pillar thicknesses tsi were simulated. The beginning part was found to unify at tsi 57 nanometer, organizing drifting organic structure consequence. The electron-hole concentration along the channel and the depletion isolation part shows different form and broaden in smaller tsi. For several channel lengths Lg = 100nm, in the decrease of pillar thickness, the sub-threshold incline ( SS ) tends to diminish, which indicate an addition in gate-gate charge yoke. Other short channel consequence parametric quantities ( Ioff, IDsat ) show better betterment for lower pillar thickness, therefore offer better public presentation and control.


With the restriction of planar lithography processing in decananometer characteristic size, perpendicular MOSFET, every bit good as other advanced constructions, was acknowledged as promising construction for farther nanoscale devices [ 1 ] . For extremist short gate length ( Lg ) up to 10s of nanometer, the channel or source/drain parts could be produced in perpendicular architecture with relaxed lithographically, alternatively of utilizing complicated, really expensive lithography tools for planar construction [ 2 ] . Furthermore, as the active country are located at the side of the Si pillar, it is easier to acquire dual or even environing gate building in perpendicular construction than in planar, therefore heightening the current thrust.

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Until late, many research workers have successfully achieved consequences for 10s of nanometre sized perpendicular construction. However, several jobs still prevail, such as the compatibility to CMOS criterion processing, high parasitic constituents and short channel consequence. By and large, several fiction techniques have been proposed, either by bed epitaxy [ 3-5 ] or by silicon pillar etch followed by ion nidation methods [ 6, 7 ] . Epitaxy method seems to be an easier manner to specify the channel part, but it faces troubles for CMOS processing for different epitaxy type in N- and PMOS. Conventional nidation method allows the CMOS compatible processing ; nevertheless crisp channel forming at the pillar was limited by either the Si pillar height itself or by the nitride spacer thickness which is applied as a mask for sidewall part [ 8 ] . The short channel effects ( SCEs ) such as threshold electromotive force ( VT ) roll-off, drain induced barrier lowering ( DIBL ) and ION/IOFF roll-off are critical at shorter Lg which determine the device public presentation, and deficiency of SCE control could forestall farther grading of the device.

Parasitic convergence electrical capacity job is normally found in perpendicular MOSFET construction that provides extra consequence on SCE. The usage of filet local oxidization ( FILOX ) technique above source/drain part was introduced to cut down the job [ 9 ] . Subsequently this work was enhanced by other plants such as by integrating dielectric pocket [ 2 ] or by presenting ORI method [ 10 ] . The later, combined with FILOX technique, was convincingly bettering the channel scaling with crisp characteristic while maintaining the parasitic electrical capacity depression. However the consequence of Si pillar decrease and the possibility of organizing to the full depleted device utilizing this method have non been to the full elaborated.

In this paper, the consequence of Si pillar thickness fluctuation on perpendicular dual gate MOSFET with FILOX and ORI method is studied. Several gate lengths, from 30-100 nanometers were compared at each pillar thickness. Gate length lower than 30nm was non selected because of the concern over the theoretical account applied in really little dimension, while the quantum consequence will come into history. The device ‘s electrical feature and its several subthreshold behavior are besides elaborated to understand the device public presentation, particularly in the presence of the short channel consequence.

Device simulation

The perpendicular MOSFET construction fiction was simulated utilizing ATHENA [ 11 ] . Silicon wafer with unvarying B doping of 1019 cm-3 was selected as base substrate. This comparatively high substrate doping gives benefit for the suppression of short channel consequence [ 12 ] . The pillar was formed by dry etch of substrate which was selectively covered by nitride as etch mask, with the breadth of nitride equal to pillar thickness tsi. In add-on, the channel length definition is affected by the tallness of pillar.

Stress alleviation oxide of 20nm was thermally grown over all silicon surface, followed by the deposition of nitride bed, which later was dry-etched anisotropically to specify the active country. Later, a thermic oxidization procedure was held to bring forth FILOX in country which was non protected by the nitride spacers ; those are the whole active country and on the top of the pillar.

The self-aligned beginning and drain part was constructed by arsenic nidation ( 6.1015 cm2, 150 keV ) utilizing Oblique Rotating Implantation ( ORI ) method. This method has shown a better form of beginning part in the underside, with the drain-to-source current flowing in pure perpendicular way [ 10 ] , instead than with non-ORI method. After etching of nitride spacers and emphasis alleviation oxide underneath, a 3-nm Si oxide bed was grown on the sidewall of pillar as a gate insulator. Later, polysilicon with unmoved doping ( As, 1019 cm-3 ) was deposited for gate electrode. Polysilicon spacer was patterned utilizing dry etch, organizing dual gate construction. After deposition of LTO for isolation, rapid thermic tempering ( RTA, 11000C, 10 s ) was carried out for dopant activation. Aluminum was used as metal contact at beginning and drain, and ohmic contact was assumed between metal and semiconducting material.

The electrical features of the device were obtained by imitating the concluding construction utilizing SILVACO ‘s ATLAS package bundle [ 11 ] . Several gate lengths ( Lg=30-100 nanometer ) at assorted Si thicknesses tsi ( 36-80 nanometer ) were applied and simulated. Heavy mesh was applied particularly for critical part such as gate oxide, dross junction and channel part. The Drift-Diffusion conveyance theoretical account with simplified Boltzmann bearer statistics was used extensively, every bit good as SRH ( Shockley-Read-Hall ) Recombination with fixed bearer life-times theoretical accounts. In the simulation, the combination of Gummel and Newton numerical methods was employed for a better initial conjecture in work outing measures for obtaining a convergence of the device construction.


The construction of perpendicular dual gate MOSFET fabricated with ORI method has been simulated and analyzed for several Si pillar thicknesses. The decrease of tsi appears to give better SCE control, manifested in the lower DIBL, better subthreshold swing, better current thrust and IDsat, while it besides has a drawback of larger escape current. The inordinate power ingestion in lower channel length was a concern, particularly for really low channel length. Furthermore, although using ORI method faces hazard of drifting organic structure consequence, which is ineluctable for Tsi & lt ; 57 nanometer, the electrical public presentation shows that cut downing pillar thickness gives more benefit in better SCE control, and besides offers better current thrust in “ON” province.

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